Optimize sum_rows_by_key() kernel by huuanhhuyn · Pull Request #3176 · NVIDIA/raft

huuanhhuyn · 2026-10-15T16:48:39Z

At lower-dimensional range (num_centroids N < 10k and hidden size K < 768), the sum_row_by_keys kernel (centroid update) accounts for a significant runtime percentage of k-means training.
We optimize this kernel to SOL at the cost of having more kernels and tuned params per architecture (code complexity).

Nsight profiling on B100

N = 1000, K = 768

N = 100, K = 128

Optimizing this kernel should improve kmeans:fit() significantly at these N and K range

Kernels

per element

the baseline (current kernel)

float4:

Each thread loads vectorized float4 and does vectorized atomic add (since Hopper)
Requires 4-byte alignments.

per warp:

One warp processed one row. Each key and weight are loaded once
Use read-only cache __ldg
Avoid the modulus % operator

sorted:

Sort rows by keys first and then sum them. Accordingly, at each moment, we sum rows of narrower key bands, allowing updates to land on L2 more often, reducing DRAM traffic.

Keep all kernels altogether allows SOL at different operational ranges (see Performance evaluation below).

Performance evaluation

A100 (sm 8.0)

float

Rows	K	N (keys)	Path	Baseline ms	Current ms	Speedup	Compute %	Memory %	L2 %	DRAM %
1M	4	1K	per element	0.128	0.128	1.00×	18.0	28.5	35.2	14.7
1M	4	10K	per element	0.069	0.083	0.83×	35.8	57.8	70.6	29.3
1M	4	100K	per element	0.057	0.057	1.00×	42.4	68.7	81.5	36.9
1M	16	1K	per element	0.176	0.176	1.00×	53.7	36.6	60.8	29.4
1M	16	10K	per element	0.176	0.176	1.00×	53.8	36.7	61.2	29.7
1M	16	100K	per element	0.176	0.176	1.00×	53.8	36.7	61.6	32.0
1M	32	1K	per element	0.343	0.343	1.00×	54.6	31.6	55.4	27.1
1M	32	10K	per element	0.343	0.343	1.00×	54.6	31.6	56.6	27.3
1M	32	100K	per element	0.343	0.343	1.00×	54.5	38.4	56.2	38.4
1M	64	1K	per warp	0.399	0.279	1.43×	68.3	47.8	82.0	40.4
1M	64	10K	per warp	0.394	0.274	1.44×	68.7	48.0	82.2	40.9
1M	64	100K	per warp	0.433	0.413	1.05×	58.4	65.7	71.5	65.7
1M	128	1K	per warp	0.792	0.398	1.99×	44.8	60.5	97.4	51.6
1M	128	10K	per warp	0.830	0.407	2.04×	46.6	62.7	98.2	55.1
1M	128	100K	per warp	0.964	0.957	1.01×	30.9	83.6	72.8	83.6
1M	768	1K	per warp	4.895	2.472	1.98×	21.0	63.6	99.3	53.8
1M	768	10K	per warp	5.452	4.857	1.12×	16.0	84.1	82.2	84.1
1M	768	100K	sorted	6.957	3.975	1.75×	18.3	62.3	98.1	62.3
1M	1536	1K	per warp	9.905	5.186	1.91×	18.5	63.8	99.5	56.7
1M	1536	10K	sorted	12.196	6.313	1.93×	14.2	54.4	90.8	47.1
1M	1536	100K	sorted	14.203	6.881	2.06×	15.9	62.2	98.1	62.2
1M	3072	1K	per warp	20.565	13.399	1.53×	17.0	72.7	99.3	72.7
1M	3072	10K	sorted	26.458	11.567	2.29×	14.4	56.6	93.6	48.9
1M	3072	100K	sorted	28.659	12.819	2.24×	15.5	62.3	97.8	62.3

double

Rows	K	N (keys)	Path	Baseline ms	Current ms	Speedup	Compute %	Memory %	L2 %	DRAM %
1M	4	1K	per element	0.103	0.103	1.00×	13.1	24.0	36.8	18.1
1M	4	10K	per element	0.042	0.042	1.00×	35.8	58.5	88.5	49.8
1M	4	100K	per element	0.042	0.043	0.98×	38.1	62.3	90.6	56.3
1M	16	1K	per element	0.118	0.126	0.94×	49.2	69.6	89.1	49.2
1M	16	10K	per element	0.117	0.117	1.00×	53.7	76.3	95.5	54.4
1M	16	100K	per element	0.171	0.170	1.01×	51.0	72.1	93.0	72.1
1M	32	1K	per element	0.218	0.224	0.97×	50.4	72.0	91.6	47.7
1M	32	10K	per element	0.220	0.220	1.00×	55.2	78.3	96.7	52.3
1M	32	100K	per element	0.424	0.424	1.00×	46.2	81.9	84.9	81.9
1M	64	1K	per warp	0.433	0.420	1.03×	44.1	80.1	96.6	51.3
1M	64	10K	per warp	0.475	0.440	1.08×	45.8	83.3	98.5	55.0
1M	64	100K	per warp	0.958	0.968	0.99×	30.5	83.0	72.7	83.0
1M	128	1K	per warp	0.812	0.910	0.89×	23.0	84.2	98.2	53.0
1M	128	10K	per warp	1.063	1.064	1.00×	23.0	84.3	98.5	66.3
1M	128	100K	per warp	2.132	2.147	0.99×	13.6	82.6	64.5	82.6
1M	768	1K	per warp	5.899	5.252	1.12×	10.3	86.7	99.3	56.7
1M	768	10K	sorted	11.790	6.405	1.84×	8.4	72.1	89.0	45.9
1M	768	100K	sorted	13.934	6.881	2.02×	9.6	82.1	97.1	61.4
1M	1536	1K	per warp	13.719	13.610	1.01×	9.6	83.3	97.6	70.4
1M	1536	10K	sorted	25.875	11.523	2.25×	9.0	78.0	93.9	49.4
1M	1536	100K	sorted	28.136	12.811	2.20×	9.5	82.6	97.3	61.9
1M	3072	1K	per warp	36.690	36.765	1.00×	7.8	79.8	84.5	79.8
1M	3072	10K	sorted	54.586	22.324	2.45×	8.8	76.6	92.8	48.4
1M	3072	100K	sorted	56.970	26.636	2.14×	9.2	80.6	96.0	62.9

H100 NVL (sm 9.0)

float

Rows	K	N (keys)	Path	Baseline ms	Current ms	Speedup	Compute %	Memory %	L2 %	DRAM %
1M	4	1K	float4	0.047	0.038	1.24×	9	31	36	16
1M	4	10K	float4	0.027	0.020	1.35×	16	56	60	27
1M	4	100K	float4	0.025	0.017	1.47×	19	69	74	34
1M	16	1K	float4	0.087	0.057	1.53×	28	49	76	33
1M	16	10K	float4	0.087	0.044	1.98×	34	59	89	41
1M	16	100K	float4	0.087	0.042	2.07×	34	60	90	45
1M	32	1K	per warp	0.170	0.170	1.00×	77	26	45	18
1M	32	10K	per warp	0.170	0.170	1.00×	77	26	45	18
1M	32	100K	per warp	0.170	0.170	1.00×	77	26	45	22
1M	64	1K	per warp	0.335	0.174	1.93×	78	45	74	31
1M	64	10K	per warp	0.335	0.174	1.93×	78	45	75	31
1M	64	100K	per warp	0.335	0.199	1.68×	73	46	71	46
1M	128	1K	per warp	0.666	0.274	2.43×	51	60	95	41
1M	128	10K	per warp	0.666	0.259	2.57×	54	64	97	44
1M	128	100K	per warp	0.667	0.403	1.66×	41	70	78	70
1M	768	1K	per warp	3.975	1.524	2.61×	23	64	98	43
1M	768	10K	per warp	3.979	1.995	1.99×	20	68	90	68
1M	768	100K	sorted	3.996	2.269	1.76×	20	62	98	51
1M	1536	1K	per warp	7.946	3.270	2.43×	20	64	99	44
1M	1536	10K	sorted	8.011	4.228	1.89×	16	56	91	39
1M	1536	100K	sorted	8.026	3.863	2.08×	18	62	97	51
1M	3072	1K	per warp	15.878	6.357	2.50×	18	64	99	50
1M	3072	10K	sorted	16.173	7.629	2.12×	16	57	92	39
1M	3072	100K	sorted	15.986	7.303	2.19×	17	62	97	51

double

Rows	K	N (keys)	Path	Baseline ms	Current ms	Speedup	Compute %	Memory %	L2 %	DRAM %
1M	4	1K	per element	0.048	0.047	1.02×	27	35	55	23
1M	4	10K	per element	0.029	0.030	0.97×	44	59	86	38
1M	4	100K	per element	0.029	0.029	1.00×	44	60	87	41
1M	16	1K	per element	0.089	0.098	0.91×	57	63	81	36
1M	16	10K	per element	0.087	0.087	1.00×	59	64	83	37
1M	16	100K	per element	0.087	0.087	1.00×	58	64	84	45
1M	32	1K	per element	0.170	0.170	1.00×	60	65	84	35
1M	32	10K	per element	0.170	0.170	1.00×	60	65	84	35
1M	32	100K	per element	0.171	0.171	1.00×	59	65	84	56
1M	64	1K	per warp	0.336	0.276	1.22×	53	79	95	41
1M	64	10K	per warp	0.335	0.264	1.27×	56	83	97	44
1M	64	100K	per warp	0.400	0.403	0.99×	43	71	80	71
1M	128	1K	per warp	0.681	0.526	1.29×	27	84	98	43
1M	128	10K	per warp	0.675	0.519	1.30×	27	85	98	47
1M	128	100K	per warp	0.906	0.909	1.00×	18	72	70	72
1M	768	1K	per warp	4.023	3.116	1.29×	11	87	99	44
1M	768	10K	sorted	4.972	4.232	1.17×	9	75	91	39
1M	768	100K	sorted	6.273	3.979	1.58×	10	83	97	51
1M	1536	1K	per warp	8.344	6.690	1.25×	10	87	99	50
1M	1536	10K	sorted	11.557	7.688	1.50×	8	76	92	39
1M	1536	100K	sorted	12.403	7.273	1.71×	9	84	97	51
1M	3072	1K	per warp	18.048	15.186	1.19×	8	82	95	66
1M	3072	10K	sorted	23.650	14.708	1.61×	8	76	91	39
1M	3072	100K	sorted	24.932	13.977	1.78×	9	84	97	52

B100 (sm 10.0)

float

Rows	K	N (keys)	Path	Baseline ms	Current ms	Speedup	Compute %	Memory %	L2 %	DRAM %
1M	4	1K	float4	0.027	0.029	0.93×	12	21	16	8
1M	4	10K	float4	0.020	0.012	1.67×	27	50	39	19
1M	4	100K	float4	0.020	0.010	2.00×	28	54	40	20
1M	16	1K	float4	0.068	0.023	2.96×	53	69	38	26
1M	16	10K	float4	0.068	0.020	3.40×	54	69	38	26
1M	16	100K	float4	0.068	0.020	3.40×	53	69	38	28
1M	32	1K	float4	0.131	0.039	3.36×	57	62	35	26
1M	32	10K	float4	0.131	0.037	3.54×	58	63	35	26
1M	32	100K	float4	0.131	0.037	3.54×	58	62	35	28
1M	64	1K	float4	0.258	0.070	3.69×	61	65	36	25
1M	64	10K	float4	0.258	0.070	3.69×	61	65	36	26
1M	64	100K	float4	0.258	0.070	3.69×	60	65	36	31
1M	128	1K	float4	0.512	0.133	3.85×	62	66	37	25
1M	128	10K	float4	0.512	0.133	3.85×	62	66	36	26
1M	128	100K	float4	0.512	0.145	3.53×	62	66	37	40
1M	768	1K	per warp	3.048	0.694	4.39×	34	94	48	33
1M	768	10K	per warp	3.053	0.725	4.21×	34	94	48	40
1M	768	100K	per warp	3.086	1.233	2.50×	32	87	54	81
1M	1536	1K	per warp	6.096	1.395	4.37×	33	96	49	33
1M	1536	10K	per warp	6.115	1.653	3.70×	33	95	49	58
1M	1536	100K	sorted	6.175	1.984	3.11×	32	90	46	38
1M	3072	1K	per warp	12.175	2.799	4.35×	33	96	49	34
1M	3072	10K	sorted	12.202	3.544	3.44×	30	89	45	32
1M	3072	100K	sorted	12.228	3.542	3.45×	31	92	47	39

double

Rows	K	N (keys)	Path	Baseline ms	Current ms	Speedup	Compute %	Memory %	L2 %	DRAM %
1M	4	1K	per element	0.023	0.037	0.62×	33	33	18	11
1M	4	10K	per element	0.020	0.016	1.25×	57	57	31	19
1M	4	100K	per element	0.020	0.016	1.25×	57	57	31	20
1M	16	1K	per element	0.068	0.061	1.11×	69	44	31	18
1M	16	10K	per element	0.068	0.061	1.11×	69	44	31	18
1M	16	100K	per element	0.070	0.061	1.15×	69	44	31	20
1M	32	1K	per element	0.131	0.115	1.14×	71	44	32	18
1M	32	10K	per element	0.131	0.115	1.14×	71	45	32	18
1M	32	100K	per element	0.131	0.119	1.10×	70	44	31	21
1M	64	1K	per warp	0.258	0.219	1.18×	64	49	36	19
1M	64	10K	per warp	0.258	0.219	1.18×	64	49	36	19
1M	64	100K	per warp	0.260	0.240	1.08×	62	47	34	29
1M	128	1K	per warp	0.512	0.238	2.15×	55	81	59	31
1M	128	10K	per warp	0.514	0.240	2.14×	55	81	59	31
1M	128	100K	per warp	0.516	0.324	1.59×	53	78	57	63
1M	768	1K	per warp	3.050	1.389	2.20×	17	86	64	33
1M	768	10K	per warp	3.063	1.628	1.88×	17	86	64	57
1M	768	100K	sorted	3.441	2.000	1.72×	17	84	62	39
1M	1536	1K	per warp	6.097	2.779	2.19×	16	87	64	33
1M	1536	10K	sorted	6.458	4.135	1.56×	14	75	55	29
1M	1536	100K	sorted	7.271	4.113	1.77×	16	86	64	39
1M	3072	1K	per warp	12.190	6.133	1.99×	16	87	64	37
1M	3072	10K	sorted	14.021	8.338	1.68×	15	78	58	30
1M	3072	100K	sorted	14.761	7.145	2.07×	16	87	65	40

RTX Pro 6000 (sm 12.0)

float

Rows	K	N (keys)	Path	Baseline ms	Current ms	Speedup	Compute %	Memory %	L2 %	DRAM %
1M	4	1K	float4	0.033	0.027	1.22×	5	46	31	46
1M	4	10K	float4	0.022	0.020	1.10×	6	60	43	60
1M	4	100K	float4	0.022	0.018	1.22×	6	60	42	60
1M	16	1K	float4	0.078	0.047	1.66×	14	87	60	87
1M	16	10K	float4	0.078	0.037	2.11×	14	87	60	87
1M	16	100K	float4	0.078	0.035	2.23×	13	85	55	85
1M	32	1K	float4	0.154	0.072	2.14×	16	91	55	91
1M	32	10K	float4	0.154	0.070	2.20×	15	89	53	89
1M	32	100K	float4	0.154	0.096	1.60×	13	86	48	86
1M	64	1K	per warp	0.301	0.178	1.69×	39	92	63	92
1M	64	10K	per warp	0.301	0.178	1.69×	39	91	63	91
1M	64	100K	per warp	0.299	0.188	1.59×	34	89	55	89
1M	128	1K	per warp	0.594	0.344	1.73×	21	94	64	94
1M	128	10K	per warp	0.594	0.344	1.73×	21	93	63	93
1M	128	100K	per warp	0.590	0.475	1.24×	15	90	45	90
1M	768	1K	per warp	3.665	2.005	1.83×	15	95	66	95
1M	768	10K	per warp	3.739	2.278	1.64×	13	89	58	89
1M	768	100K	sorted	5.925	2.910	2.04×	11	87	51	87
1M	1536	1K	per warp	7.771	4.000	1.94×	14	96	67	96
1M	1536	10K	sorted	8.929	4.744	1.88×	13	89	61	89
1M	1536	100K	sorted	12.521	5.537	2.26×	11	87	51	87
1M	3072	1K	per warp	14.904	8.028	1.86×	14	95	67	95
1M	3072	10K	sorted	20.515	9.079	2.26×	13	89	61	89
1M	3072	100K	sorted	25.633	10.732	2.39×	11	88	51	88

double

Rows	K	N (keys)	Path	Baseline ms	Current ms	Speedup	Compute %	Memory %	L2 %	DRAM %
1M	4	1K	per element	0.037	0.037	1.00×	15	63	47	63
1M	4	10K	per element	0.022	0.025	0.88×	19	85	64	85
1M	4	100K	per element	0.022	0.022	1.00×	17	80	57	80
1M	16	1K	per element	0.086	0.086	1.00×	27	91	76	91
1M	16	10K	per element	0.088	0.086	1.02×	27	91	75	91
1M	16	100K	per element	0.098	0.094	1.04×	24	88	67	88
1M	32	1K	per element	0.180	0.180	1.00×	30	94	83	94
1M	32	10K	per element	0.180	0.180	1.00×	29	93	82	93
1M	32	100K	per element	0.190	0.190	1.00×	25	89	71	89
1M	64	1K	per warp	0.346	0.346	1.00×	25	90	82	90
1M	64	10K	per warp	0.346	0.346	1.00×	25	90	81	90
1M	64	100K	per warp	0.469	0.469	1.00×	18	88	59	88
1M	128	1K	per warp	0.680	0.680	1.00×	26	91	85	91
1M	128	10K	per warp	0.680	0.680	1.00×	26	92	85	92
1M	128	100K	per warp	1.382	1.396	0.99×	13	92	44	92
1M	768	1K	per warp	4.382	4.002	1.09×	27	95	90	95
1M	768	10K	sorted	6.346	4.743	1.34×	24	85	78	85
1M	768	100K	sorted	11.571	5.466	2.12×	21	88	69	88
1M	1536	1K	per warp	8.560	8.005	1.07×	27	96	90	96
1M	1536	10K	sorted	17.569	9.116	1.93×	23	84	77	84
1M	1536	100K	sorted	24.013	10.627	2.26×	21	89	70	89
1M	3072	1K	per warp	17.747	17.597	1.01×	25	90	82	90
1M	3072	10K	sorted	41.464	17.639	2.35×	24	86	79	86
1M	3072	100K	sorted	48.842	20.958	2.33×	21	89	70	89

- load key once per row (one warp takes one row) - Use read-only cache __ldg - Avoid expensive % operator

coderabbitai · 2026-10-15T16:56:36Z

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📝 Summary

Summary by CodeRabbit

Performance
- Improved row-major reductions with large key counts by selecting a processing approach based on row width, data type, alignment, device capabilities, and workload size.
- Suitable large workloads can use a sorting-based approach to improve reduction performance.
- Wider rows can use aligned vector processing when supported, while other workloads retain approaches suited to their data and device.

The large-key row-major reduction now selects among per-element, float4, per-warp, and radix-sorted per-warp kernels. The dispatcher accepts nkeys and uses input dimensions and device properties to select a path.

Changes: Large-key row-major reduction

Layer / File(s)	Summary
Row-major reduction kernels `cpp/include/raft/linalg/detail/reduce_rows_by_key.cuh`	The per-element kernel remains available. New float4 and per-warp kernels reduce row-major inputs. The per-warp kernel supports optional row-ID indirection.
Sorted per-warp reduction `cpp/include/raft/linalg/detail/reduce_rows_by_key.cuh`	The sorted path creates uint32 key and row-ID arrays, radix-sorts pairs by key, then invokes the per-warp reducer. The path checks index limits and input and output size thresholds.
Path selection and call wiring `cpp/include/raft/linalg/detail/reduce_rows_by_key.cuh`	The planner selects a kernel using alignment, column count, row width, size thresholds, and device properties. The dispatcher and its call site now pass `nkeys`.

Priority: Normal

Estimated code review effort: 3 (Moderate) | ~25 minutes

Change: Refactor

Suggested reviewers: viclafargue

Merge Risk: Low · previous review f1f3b

The new kernel paths speed up the lower-dimensional range. Two small robustness issues remain: a possible compile error for 32-bit index types, and a potential index wrap for extremely large row counts. Both are narrow and easy to fix, so merge risk is low.

Pre-merge checks: 5

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Title check		The title clearly and concisely describes the main change: optimizing the sum_rows_by_key() kernel.
Description check		The description directly explains the optimization of the sum_row_by_keys centroid-update kernel and matches the added per-element, float4, per-warp, and sorted kernel paths.

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Review comments at @cpp/include/raft/linalg/detail/reduce_rows_by_key.cuh:
- Around line 330-331: Update the warp-index calculations and grid-stride loop
in the warp kernel to use 64-bit arithmetic throughout, including casts of CUDA
dimension values before multiplication and conversion of nrows for the loop
comparison. This prevents overflow in warp_id and n_warps for large row counts.

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cpp/include/raft/linalg/detail/reduce_rows_by_key.cuh

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viclafargue

Thanks for the PR and the detailed performance measurements! The changes look good to me. Approved.

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cpp/include/raft/linalg/detail/reduce_rows_by_key.cuh: 1
336-338: 🎯 Functional Correctness | 🟡 Minor | ⚡ Quick win

Compute warp_id and n_warps in 64-bit arithmetic.

static_cast<IdxT>(gridDim.x) * blockDim.x is computed in unsigned int when IdxT is int. The launcher can create up to 1 << 30 blocks of 128 threads. The product then wraps to a smaller value or to zero. If n_warps becomes zero, the grid-stride loop does not advance. Otherwise, the kernel can compute wrong warp indices and visit rows twice. Use std::int64_t for warp_id, n_warps, and the loop index.
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Review comment at @cpp/include/raft/linalg/detail/reduce_rows_by_key.cuh around
lines 336 - 338:
Update the warp-stride loop in the visible kernel to use std::int64_t for
warp_id, n_warps, and the loop index, ensuring the block/grid arithmetic is
promoted to 64-bit before multiplication so large grids produce correct warp
indices and a nonzero stride.

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Duplicate comments:
Review comments at @cpp/include/raft/linalg/detail/reduce_rows_by_key.cuh:
- Around line 336-338: Update the warp-stride loop in the visible kernel to use
std::int64_t for warp_id, n_warps, and the loop index, ensuring the block/grid
arithmetic is promoted to 64-bit before multiplication so large grids produce
correct warp indices and a nonzero stride.

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…6-byte alignments

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Inline comments:
Review comments at @cpp/include/raft/linalg/detail/reduce_rows_by_key.cuh:
- Line 600: Replace the list-initialization of the `ceildiv` divisor with an
explicit cast from `plan.block_dim` to `IdxT` at both call sites, including the
calls using `nvecs` and `nrows * ncols`.

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cpp/include/raft/linalg/detail/reduce_rows_by_key.cuh

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huuanhhuyn · 2026-10-19T11:02:02Z

Many thanks @viclafargue and @divyegala for having a look. I have added new kernels and tuning logics since your last looking. It would help if you could review again.

divyegala · 2026-10-21T17:41:00Z

 template <typename DataIteratorT,
          typename KeysIteratorT,
          typename WeightT,
          typename SumsT,


Should we add a static check that SumsT does not narrow WeightT and that both types belong to the same numeric type family?

This is to make sure casts like this don't cause accidental side-effects https://github.com/NVIDIA/raft/pull/3176/changes#diff-ee891f4e924cc29da43803011dfcae91ee2bcec531ba7a447cd0fa2ea5da6e01R376

I also don't see any circumstance where we want give weight type more precise or even of a different family type than the sum. I can add it.

Added it cf53129.

I assume we still want to allow integer weight type with float sum type. Besides it, integers of different sizes should be fine as they don't cause precision issue.
-> So we throws when both are floats and SumsT does not narrow WeightT.

tfeher

Thanks Huy for the PR! Here are my first comments:

tfeher · 2026-10-22T09:48:44Z

+#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 900
+  // vectorized atomic add only available since Hopper
+  atomicAdd(reinterpret_cast<float4*>(dst), a);
+#else
+  raft::myAtomicAdd(dst, a.x);
+  raft::myAtomicAdd(dst + 1, a.y);
+  raft::myAtomicAdd(dst + 2, a.z);
+  raft::myAtomicAdd(dst + 3, a.w);
+#endif


Please create a variant of myAtomicAdd in utils/cuda_utils.cuh for the vectorized type.

Yes, added it cc4af47

tfeher · 2026-10-22T09:48:48Z

+  a.x *= w;
+  a.y *= w;
+  a.z *= w;
+  a.w *= w;


Can we use our vectorization helper struct here?

raft/cpp/include/raft/util/vectorized.cuh

Lines 253 to 295 in 021cddc

* @struct TxN_t

*

* @brief Internal data structure that is used to define a facade for vectorized

* loads/stores across the most common POD types. The goal of his file is to

* provide with CUDA programmers, an easy way to have compiler issue vectorized

* load or store instructions to memory (either global or shared). Vectorized

* accesses to memory are important as they'll utilize its resources

* efficiently,

* when compared to their non-vectorized counterparts. Obviously, for whatever

* reasons if one is unable to issue such vectorized operations, one can always

* fallback to using POD types.

*

* Concept of vectorized accesses : Threads process multiple elements

* to speed up processing. These are loaded in a single read thanks

* to type promotion. It is then reinterpreted as a vector elements

* to perform the kernel's work.

*

* Caution : vectorized accesses requires input addresses to be memory aligned

* according not to the input type but to the promoted type used for reading.

*

* Example demonstrating the use of load operations, performing math on such

* loaded data and finally storing it back.

* @code{.cu}

* TxN_t<uint8_t,8> mydata1, mydata2;

* int idx = (threadIdx.x + (blockIdx.x * blockDim.x)) * mydata1.Ratio;

* mydata1.load(ptr1, idx);

* mydata2.load(ptr2, idx);

* #pragma unroll

* for(int i=0;i<mydata1.Ratio;++i) {

* mydata1.val.data[i] += mydata2.val.data[i];

* }

* mydata1.store(ptr1, idx);

* @endcode

*

* By doing as above, the interesting thing is that the code effectively remains

* almost the same, in case one wants to upgrade to TxN_t<uint16_t,16> type.

* Only change required is to replace variable declaration appropriately.

*

* Obviously, it's caller's responsibility to take care of pointer alignment!

*

* @tparam math_ the data-type in which the compute/math needs to happen

* @tparam veclen_ the number of 'math_' types to be loaded/stored per

* instruction

Yes, we reused it now cc4af47

tfeher · 2026-10-22T10:06:40Z

+{
+  rmm::device_uvector<uint32_t> keys(nrows, st), row_ids(nrows, st);


This can be problematic if we have a large number of rows (e.g. billions). Do we have an upper limit (e.g. due to batching up the problem before calling the reduction?

In that case the training set is already very large 1B * n_cols. These are just 2 additional columns to the training set effectively. This method is called for the case with a large number of columns, e.g. 1024.

The added allocations from radix sorting is nrows * dtype * 4 + small buffer. There is also a dry-run unit test for it now 1113f2b

@tfeher @achirkin I added the batching up to 4M rows.

achirkin · 2026-10-26T09:48:00Z

+  const IdxT vecs_per_row = ncols / 4;
+  const IdxT i            = q / vecs_per_row;
+  const IdxT j            = (q - i * vecs_per_row) * 4;
+  float4 a                = __ldg(reinterpret_cast<const float4*>(d_A + lda * i + j));


Could you try to implement this with raft's vectorised types instead https://github.com/NVIDIA/raft/blob/main/cpp/include/raft/util/vectorized.cuh ?

Then use https://github.com/NVIDIA/raft/blob/main/cpp/include/raft/util/device_loads_stores.cuh for explicit cache behavior and https://github.com/NVIDIA/raft/blob/main/cpp/include/raft/util/device_atomics.cuh for the atomics below

Thanks Artem. I didn't even know those libraries existed.

vectorized.cuh -> I reused it cc4af47

device_loads_stores.cuh -> It uses L2-cached load ld.global.cg. I am using the theoretically faster read-only ld.global.nc variant. Also, I reused the load() method in vectorized.cuh so __ldg is gone now.

device_atomics.cuh -> It uses atomicCAS, which is significantly slow under high contention. The current kernel is using native atomicAdd.

Because this kernel has performance priority, I wouldn't use the last two libraries. Extending the libraries would also be quite awkward.

huuanhhuyn · 2026-10-27T19:11:48Z

@tfeher @achirkin @divyegala The PR is RFR again.

Optimize sum_rows_by_key kernel

666a617

- load key once per row (one warp takes one row) - Use read-only cache __ldg - Avoid expensive % operator

huuanhhuyn requested a review from a team as a code owner October 15, 2026 16:48

github-project-automation Bot added this to Unstructured Data Processing Oct 15, 2026

Keep the old kernel for K <=32. It is more optimized for that range.

7658a18

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Comment thread cpp/include/raft/linalg/detail/reduce_rows_by_key.cuh Resolved

huuanhhuyn changed the title ~~Improve kmeans::fit() performance via optimizing the row summing kernel~~ Improve kmeans::fit() low-dimensional performance Oct 16, 2026

huuanhhuyn changed the title ~~Improve kmeans::fit() low-dimensional performance~~ Improve kmeans::fit() performance at lower-dimensional range (centroids, columns) Oct 16, 2026

huuanhhuyn changed the title ~~Improve kmeans::fit() performance at lower-dimensional range (centroids, columns)~~ Improve kmeans::fit() performance at lower-dimensional range Oct 16, 2026

viclafargue approved these changes Oct 16, 2026

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github-project-automation Bot moved this to Approved in Unstructured Data Processing Oct 16, 2026

huuanhhuyn added 2 commits October 16, 2026 11:06

Extra kernel - Sort rows by key before summing

82fa848

Merge remote-tracking branch 'origin/main' into improve_kmeans_fit

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divyegala and others added 2 commits October 16, 2026 13:23

Merge branch 'main' into improve_kmeans_fit

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Merge branch 'main' into improve_kmeans_fit

cad9556

huuanhhuyn changed the title ~~Improve kmeans::fit() performance at lower-dimensional range~~ [WIP] Improve kmeans::fit() performance at lower-dimensional range Oct 19, 2026

huuanhhuyn added 2 commits October 19, 2026 10:00

Add vectorized load kernel - improve latency-bound at K < 64, given 1…

d6e7877

…6-byte alignments

Single kernel selection point. Tune params.

f1f3b67

huuanhhuyn changed the title ~~[WIP] Improve kmeans::fit() performance at lower-dimensional range~~ Improve kmeans::fit() performance at lower-dimensional range Oct 19, 2026

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Comment thread cpp/include/raft/linalg/detail/reduce_rows_by_key.cuh Resolved

Fix code rabbit

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achirkin added improvement Improvement / enhancement to an existing function non-breaking Non-breaking change labels Oct 20, 2026

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github-project-automation Bot moved this from Approved to In Progress in Unstructured Data Processing Oct 22, 2026

viclafargue mentioned this pull request Oct 22, 2026

Make k-means fit deterministic NVIDIA/cuvs#2801

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aamijar mentioned this pull request Oct 22, 2026

[TRACKER] CI Test Failures Needing attention NVIDIA/cuvs#2118

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18 of 22 tasks

huuanhhuyn changed the title ~~Improve kmeans::fit() performance at lower-dimensional range~~ Optimize sum_rows_by_key() kernel Oct 26, 2026

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sherylll mentioned this pull request Oct 27, 2026

Add Super K-Means NVIDIA/cuvs#2948

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huuanhhuyn added 5 commits October 27, 2026 12:17

Static assert weight and sum types

cf53129

Reuse / extend libraries.

cc4af47

Dry-run compliance. No dry-run tests

30da49c

Clang-format

68538fe

Merge branch 'main' into improve_kmeans_fit

18d4d8a

This was referenced Oct 28, 2026

Use the small-nkeys kernel of reduce_rows_by_key only with few columns #3194

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Coalesced small-nkeys kernel for reduce_rows_by_key #3195

Open

Portable array-API KMeans estimator with native PyTorch and CuPy updates ogrisel/cursor-sandbox#17

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huuanhhuyn requested review from achirkin and tfeher October 28, 2026 10:27

huuanhhuyn added 2 commits October 29, 2026 12:19

Dry-run unit test for allocating path (sorted variant)

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Merge branch 'main' into improve_kmeans_fit

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bdice mentioned this pull request Oct 29, 2026

[CI] Flaky test sweep (Sep–Oct 2026): root causes and fix PRs NVIDIA/cuvs#2783

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d858619

	* @struct TxN_t
	*
	* @brief Internal data structure that is used to define a facade for vectorized
	* loads/stores across the most common POD types. The goal of his file is to
	* provide with CUDA programmers, an easy way to have compiler issue vectorized
	* load or store instructions to memory (either global or shared). Vectorized
	* accesses to memory are important as they'll utilize its resources
	* efficiently,
	* when compared to their non-vectorized counterparts. Obviously, for whatever
	* reasons if one is unable to issue such vectorized operations, one can always
	* fallback to using POD types.
	*
	* Concept of vectorized accesses : Threads process multiple elements
	* to speed up processing. These are loaded in a single read thanks
	* to type promotion. It is then reinterpreted as a vector elements
	* to perform the kernel's work.
	*
	* Caution : vectorized accesses requires input addresses to be memory aligned
	* according not to the input type but to the promoted type used for reading.
	*
	* Example demonstrating the use of load operations, performing math on such
	* loaded data and finally storing it back.
	* @code{.cu}
	* TxN_t<uint8_t,8> mydata1, mydata2;
	* int idx = (threadIdx.x + (blockIdx.x * blockDim.x)) * mydata1.Ratio;
	* mydata1.load(ptr1, idx);
	* mydata2.load(ptr2, idx);
	* #pragma unroll
	* for(int i=0;i<mydata1.Ratio;++i) {
	* mydata1.val.data[i] += mydata2.val.data[i];
	* }
	* mydata1.store(ptr1, idx);
	* @endcode
	*
	* By doing as above, the interesting thing is that the code effectively remains
	* almost the same, in case one wants to upgrade to TxN_t<uint16_t,16> type.
	* Only change required is to replace variable declaration appropriately.
	*
	* Obviously, it's caller's responsibility to take care of pointer alignment!
	*
	* @tparam math_ the data-type in which the compute/math needs to happen
	* @tparam veclen_ the number of 'math_' types to be loaded/stored per
	* instruction

		{
		rmm::device_uvector<uint32_t> keys(nrows, st), row_ids(nrows, st);

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Nsight profiling on B100

Kernels

Performance evaluation

A100 (sm 8.0)

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double

H100 NVL (sm 9.0)

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double

B100 (sm 10.0)

float

double

RTX Pro 6000 (sm 12.0)

float

double

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