Repository navigation

CPU-Verilog-Design

Public

About

Verilog MIPS CPU design and verification project

0 stars

1 watching

Name		Name	Last commit message	Last commit date
ALU.v		ALU.v
ALUOut_register.v		ALUOut_register.v
A_register.v		A_register.v
B_register.v		B_register.v
CPU.v		CPU.v
CPU_test.v		CPU_test.v
Control.v		Control.v
Control_tb.v		Control_tb.v
DMem.v		DMem.v
IMem.v		IMem.v
Instruction_register.v		Instruction_register.v
JumpAddress.v		JumpAddress.v
MemoryData_register.v		MemoryData_register.v
Multi-Cycle CPU Final Report.pdf		Multi-Cycle CPU Final Report.pdf
PC32bit.v		PC32bit.v
README.md		README.md
aluControl.v		aluControl.v
mux2.v		mux2.v
mux3.v		mux3.v
mux4.v		mux4.v
nbit_register_file.v		nbit_register_file.v
signextender.v		signextender.v
truncate32to16.v		truncate32to16.v
zeroextender.v		zeroextender.v

Verilog MIPS CPU design and verification project

0 stars

1 watching